Internships/Co-Ops

@jeremy-hunt

[2025 Internship] Physical Verification CAD Intern II (PTD/CAD)

With guidance, you will work within CAD team to code in-house rule using Calibre Standard Verification Rule Format (SVRF). You will collaborate with process development kit team for the test … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] Machine Learning Algorithm Engineer Intern (CAI2)

[What you will do] - Develop Machine Learning/Deep Learning algorithm for machine vision/natural language processing - Develop new applications (Android App) in the next generation smartphone, surveillance, smart home and … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] IC Layout Engineer Intern [PTD/LO]

MediaTek Layout team is looking for suitable candidates to design IC layout for Foundation and Analog/RF IP developments. [What you will do] - Design layout for Foundation (Standard Cell) and … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] Full Stack Software Intern (PTD/CAD)

• Assist in maintenance, enhancement, and development of web applications in CMS. • Responsible for Drupal development and configuration on custom application build • Perform database query, analyze and clean … Read More Read More

Categories:

Software

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] Physical Verification CAD Intern I (PTD/CAD)

When you join us, you’ll work alongside with experienced engineers who’ll mentor and guide you. You will be involved in: • Learn design rule check coding • Execute design rule … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] Physical Verification Sign-off Intern (PTD/CAD)

When you join us, you’ll work alongside with experienced engineers who’ll mentor and guide you. You will be involved in: • Execute design rule checks on real chip design • … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] Timing Signoff Engineer (CAI2/3)

• Work on timing sign off, convergence, automations and methodology development. • Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. • Run Primetime and/or Tempus for STA … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] Analog Design Intern - Power Management Circuit (ACD7)

- Design of Analog/Mixed-signal IC circuit blocks / IPs based on specifications (performance, area, power consumption) for a variety of smart phones, IoT, automotive, and ASIC products. - Realize IC … Read More Read More

Categories:

Management

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] NPU Physical Implementation Intern (CAI3)

[What you will do] Scripting and flow automation for NPU Physical Implementation Design one system to do data mining for all existing NPU design and Provide recommendations for later new … Read More Read More

Category:

Chip Design

Jeremy Hunt

@jeremy-hunt

[2025 Internship] IC Physical Design (SPD5)

- Responsible for physical design, development of variety of SoC(System On Chip) and tapeout. - Execute state-of-art methodologies include synthesis, floor-planning, place and route, RC extraction, timing and power optimization, … Read More Read More

Category:

Chip Design